Shrinking ferroelectric tunnel junctions can significantly boost their performance in memory devices, as reported by researchers from Science Tokyo. The team fabricated nanoscale junctions directly on silicon substrates and analyzed conduction mechanisms across a wide temperature range and multiple device scales. They found that smaller junction areas produced much larger resistance contrasts between the "ON" and "OFF" states, demonstrating that miniaturization could directly improve both efficiency and reliability in future non-volatile memory technologies.